Analog / Mixed Signal IC Design Engineer - PLLs - Southern Germany
This is a new and exciting opportunity for an Analog IC Design Engineer to join a global leader in Semiconductor development for consumer applications. Based in the highly desired city of Munich, the Analog/Mixed Signal IC Design Engineer will be working within an international team on the design and architecture of PLLs.
Your tasks will include specification, test plans, frequency-domain PLL loop analysis, simulation, Design, floor planning and Layout, checks required before IP release as well as review of silicon results for characterisation for PLLs.
The successful candidate will be industry degree qualified with proven experience in Analog or Digital PLL's for frequency synthesis or SerDes applications, specifically including PLL loop dynamics and building blocks, jitter sources and modelling. Experience with some of the following PLL sub-blocks is essential: charge-pump, loop-filter, VCO/DCO, regulators, references, high-speed dividers, level-shifters, synchronizers, PFD/TDC. The role also requires a good understanding of verification flows as well as experience in some of the following scripting languages: C, C++, Perl, Python, Matlab, Verilog A, UNIX Shell.
Additionally, experience in DFT techniques and production test, PLL related integration (ESD, package, board design), calibration, fast-lock, spur-cancellation, LC-VCO, basic ADC/DAC, FinFet technology in design and layout, RTL, digital loop filters and delta-sigma modulators are of advantage to your application.
Good communications skills in English are essential.
Contact Ane today for further information and to apply!
Applicants with experience in: Analog / Mixed Signal IC Design, PLLs, SERDES, charge-pump, loop-filter, VCO, DCO, regulators, references, high-speed dividers, level-shifters, synchronizers, PFD, TDC, C, C++, Perl, Python, Matlab, verilogA, ADC, DAC, FinFet, RTL will be considered. Location: Munich, Germany