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Digital ASIC Design Engineer – Grenoble

Digital ASIC Design Engineer - Low power IoT

An excellent new career opportunity for a Digital ASIC Design Engineer has arisen with an expanding Semiconductor start-up based in Grenoble.

This is a superb opportunity if you are a Digital RTL Design Engineer with a solid background in either ASIC or FPGA development, and keen to push your career forward within innovative new wireless technology company. You will be working on ultra long range, low power consumption radio interface technologies for the Internet of Things domain.

The role:
As the successful Digital ASIC Design Engineer you will be involved in the complete ASIC design flow process, from architecture definition, RTL development of signal processing functions through synthesis and validation on FPGA, to supporting physical synthesis, layout and chip sign off.


Successful applicants will be degree qualified in a relevant subject area such as Computing or Electronics and have proven experience working in Digital ASIC / FPGA Design, with skills in at least some of the following:

-Digital RTL coding
-VHDL, Verilog or SystemVerilog
-Design architecture and specification
-ASIC Verification
-Synthesis / STA
-Use of EDA tools (Mentor / Synopsys / Cadence)
-Experience working in wireless telecommunications would be a benefit, but not essential.

For more information or to apply please contact Caroline @ IC Resources.

Grenoble based opportunity for a Digital ASIC Design Engineer with skills in: Digital, ASIC, FPGA, Design, IC, SoC, system on chip, RTL, integrated circuit, junior, senior, verification, synthesis, STA, VHDL, Verilog, Verification, wireless, telecommunications, MAC, WiFi, signal processing, hardware, EDA, Cadence, Synopsys, Mentor, Grenoble, France, job, career.


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Job Details
  • €45000 - €60000 per annum + upon experience
  • Grenoble,France
  • Permanent
  • J37436_icr
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