Digital Physical Implementation Engineer - ASIC Physical Design, Cambridge
This is a new opportunity for an up and coming Digital Physical Implementation Engineer with our global electronics client in Cambridge.
The right candidate for this position will have a keen interest in Physical Implementation for digital ICs, with knowledge of ASIC design flow, and ideally some experience in at least two areas of implementation: Synthesis/Equivalence Checking, DFT/ATPG insertion, Low Power Design Methodologies, Place and Route, STA and/or Stakeout.
As the Physical Implementation Engineer you will work alongside senior engineers on the RTL2GDS implementation of mixed signal chip for wireless devices. You will be responsible for chip implementation, ensuring that chips are taped out on time and to quality standards, and be
responsible for continually improving quality standards and team productivity.
The right candidate for this role might have a couple of years' experience in industry, or potentially be recently PhD-qualified with no prior industrial experience.
On offer is a generous remuneration package: a highly competitive basic salary together with RSS, plus comprehensive benefits.
Contact Caroline @ IC Resources today for details.
Key words: Digital, Implementation, Physical Design, ASIC, Backed, Physical Implementation, RTL, ASIC, Verilog, VHDL, GDS2, GDSII, RTL-GDSII, , Place & Route, routing, P&R, PNG, synthesis, clock tree, stakeout, timing closure, STA, static timing analysis, Soc., DFT, design for test, EDA, Synopsis, Cadence, clock tree synthesis, CTS, physical verification, netlist, CAD, CMOS, Semiconductor, Cambridge, South East, East Anglia, UK.