Based in Paris the FPGA Design Engineer will be responsible for leading a team on the design, development and validation of high speed, low latency digital circuits targeting a high end FPGA's , for the real time processing of financial market data.
Other responsibilities will include participate in product definition and project planning and algorithm design and system-level architecture.
The successful candidate will have a good relevant degree, with a background in Team Leading FPGA Design Engineers. Other requirements include:
* Proven high speed FPGA Design up to 250MHz and above
* Strong VHDL experience
* An understanding of low-latency digital circuits, targeting a high-end FPGA, for the real-time processing of financial market data would be beneficial
* The successful candidate will be highly autonomous, good at communicating in both French and English, able to multi-task and adapt to changeable priorities.
FPGA, VHDL, Team Lead, Financial, Paris