Hardware Design Engineer
This is an opportunity to join a newly founded RTL design team set up for the purpose of creating Vision Processing intellectual property complementary to the existing range of PowerVR products. The successful candidate will become part of a dynamic and motivated design team working on the full design cycle from specification and implementation through to verification. The job will include exposure to cutting edge EDA tools and advanced silicon processes.
- The role will involve working alongside a Senior Engineer and with the System Architect to define module level architectures and documenting these module specifications
- Converting the architecture into RTL while considering constraints such as area, speed, power and performance
- Verification of the RTL at module level and top level in conjunction with the simulator group using state of the art verification methodologies
- Synthesis and formal verification
- Power and performance analysis
Work alongside a Senior Engineer to develop state of the art Vision Processing blocks to complement PowerVR’s Video and Graphics cores. These IP cores used by top tier semiconductor suppliers to produce highly integrated SOC’s.
You will be working at the leading edge of ASIC design with the most advance algorithms and methodology.
Target Capabilities and Skills
- Able to work well as part of a team
- Approachable with motivating communication and interpersonal skills
- Excellent problem solving abilities
- Technical excellence is very important and the desire to be responsible for a design for which you take pride in
You will be directly working in a small team which is part of a larger PowerVR Video Hardware Group.
Ideally qualified as a minimum to degree level with Honours at either 1st or 2.1. Other qualifications would also be suitable if they are at least equivalent.
- An excellent knowledge of digital design techniques, including high speed and low power design.
- You must be proficient in RTL design with previous experience coding in VHDL or verilog.
- You must be familiar with the whole ASIC design process and have a clear understanding of SOC architecture.
- Previous experience with synthesis, formal verification and power compiler is highly desirable.
- Experience working in video is highly desirable.
- Video/Vision experience or knowledge
- Scripting: Perl, TCL, make and cshell
- Familiar with unix/linux working environment
- Familiar with emulator and FPGA systems
Hertfordshire, South East EnglandPrintSave To Shortlist