Senior Analog IC Design Engineer - SERDES - Switzerland
A new opportunity has arisen for an experienced Analog IC Design Engineer to joining an expanding company based in the scenic and highly desired French speaking part of Switzerland.
In this position you will be responsible for the Design of Analog ICs for high speed links (SerDes) working in advanced process nodes.
* Block level specifications of high speed Analog circuits that meet key performance targets based on system level requirements
* Design, layout and verification of Analog circuits
* Supporting IP and chip level integration
* Guiding the layout team and mentoring junior engineers
* Support lab characterisation, debug/test
* Customer support on requirements, design specs and product delivery.
Industry degree qualified, the successful Analog IC Design Engineer will have established experience ideally in multi-gigabit serial data-link transceivers such as CDR (clock and data recovery circuits), output drivers, equalizers, clock generators and samplers. Expertise in design and layout of high-speed circuits like amplifiers, oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks such as biasing, buffers, regulators, filters, data converters is ideal. It would be advantageous to have experience on modern process nodes down to 14nm/16nm.
Strong design and verification tools experience is required in; Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modeling, EM and IR drop. Experience in high-level modeling, top-level simulations, ESD checks will be a plus.
You will be self motivated with strong sense of ownership and responsibility. Good communication skills in English is ideal with knowledge in the French language an asset.
Key words: Analog, Mixed Signal, IC Design, multi-gigabit, Gb/s, clock and data recovery circuits, serial data-link transceivers, CDR (clock and data recovery circuits), output drivers, equalizers, clock generators, samplers, high-speed circuits, amplifiers, oscillators, PLLs, phase-locked loops, DLLs, delay-locked loops, biasing, buffers, regulators, filters, ADCs, finFET, 14nm/16nm. Location: French speaking part of Switzerland.