Senior DDR PHY Design Engineer
Our client, one of the world's biggest names in consumer electronics is looking for a Senior DDR PHY Design Engineer to join their new Munich design team.
In this role, you will be at the centre of a PHY design effort working closely with architecture, CAD, timing and PD design teams, having a a critical impact on delivering best in class PHY designs. You will be responsible for all phases of PHY design of high performance DDR interface from architecture, RTL to delivery of final GDSII.
As the ideal candidate you will be degree-qualified in Electronics or related field, and have at least 5 years of DDR PHY Design experience on high performance, low power SOC designs. You will be knowledgeable in the following:
*RTL design in VHDL or Verilog
*Scripting languages such as Perl/Tcl.
*Extraction and STA (Static Timing Analysis) methodology and tools
Design methodology to debug issues at PHY level
You will be a team player will excellent written and verbal communication skills in English and with German language skills an asset.
Applicants with the following skills; Digital, SoC, ASIC, RTL, PHY, DDR, Physical Layer, VHDL, Verilog, verification, synthesis, architecture, scripting, tlc, Perl. Location: Munich Germany.
Please note, candidates must be eligible to work in Germany to apply.
For more details, please contact Caroline @ IC Resources