Senior Digital ASIC Design Engineer - High Speed Serdes - UK
A UK based division of a leader in the development of energy efficient communication applications is looking for an experienced Digital ASIC Design Engineer to join their team in the East Midlands of England.
In this role you will be working on High Speed Serdes designs in Finfet technology 16nm and below.
The successful candidate will have:
*Hands on experience in coding RTL, Verilog preferably for Serdes IP, DDR interfaces, Ethernet switches or SoC in multi-GHz range flip-chip package designs.
*Skilled at design optimization, timing closure and power optimization of high speed digital logic in advanced process nodes (7-28nm) through the logic implementation loop (synthesis, P&R) using industry standard tools and flows (Cadence, Synopsys, Magma, etc).
*Knowledge of digital IC verification flows, System Verilog assertions, functional coverage, DFT, Scan, etc.
*Experience in IP deployment, support, test and characterization would be advantageous.
A competitive salary is on offer, with a very good stock option programme.
For details, please contact Caroline @ IC Resources.
Applicants with experience in: Digital IC Design, ASIC Design, SoC, RTL, VHDL, Verilog, IP, timing closure, backend, physical, power optimisation, implementation, synthesis, Place & Route, P&R, EDA, SystemVerilog, High Speed Serdes, Finfet, 16nm, Ghz, Gb/s, physical layer, PHY. Location: East Midlands of England.