Senior Digital Verification Engineer - Villach, Austria
A Verification Engineer with excellent complex verification skills (SystemC, systemVerilog, UVM) is sought for a challenging and varied role within a leading provider of semiconductors and system solutions for automotive and industrial electronics & chip card and security applications.
You will be part of an international team with interfaces to concept engineers as well as analog and digital designers, and will have responsibility over the verification methodology. This exciting opportunity involves the creation and maintenance of verification plans, defining verification metrics and setting up verification environments and executing tests at RTL and gate-level.
The ideal candidate will;
*Have at least 3 years experience in pre-silicon verification
*Have an in-depth knowledge and project experience of systemVerilog, Verilog, VHDL, OVM, UVM and/or SVA
*Have a good knowledge of Unix programming languages such as shell, Perl and TCL
Any knowledge of PSL, SystemC, property checking and mixed-signal verification would be beneficial, but is not required.
You will be a talented leader, able to communicate well with all internal and external groups, with a great team spirit and drive to get things done. Fluent English is essential; any German language skills would be a bonus.
This is a unique opportunity to join a rapidly expanding company offering fantastic career and skills development opportunities, as well as an exceptional salary and company benefits package.
Keywords: Digital, ASIC, SoC, Hardware, Software, Verification, RISC, Specman e, Microprocessor, ARM, EDA, UNIX, LINUX, Tcl, Perl, SystemC, Vera, Specman e, E Language, C, C++, IC Design, testbench, testplan, object oriented, constrained random, ABV, scoreboard, RTL simulation, travel, cadence, mentor graphics, Synopsys, Xilinx, Altera, Microsemi, Lattice, FPGA, RTL, Design, OVM, VMM, UVM, SystemVerilog, VHDL, Verilog, testbench, Semiconductor, Villach, Graz, Europe