Senior IC Verification Lead - Munich
This is a new and exciting opportunity for a Senior IC Verification Leader to join a IC Design Group for global leader of low-power consumer electronics devices.
Within the Munich-based design centre, you will assume a technical, hands-on management role. managing a verification team interfacing with the engineering design team and developing the verification environment for new silicon developments.
Manage the verification team, including taking responsibility for hiring, resource planning, scheduling, communication with upper management and overall verification team execution.
Take responsibility for performance management of individual team members.
Take responsibility for all aspects of verification methodology
Work closely with the design team to review specifications, understand chip architecture, develop tests & coverage plans, define methodology & test benches.
Design Verification - Implement testbenches, run regressions at RTL and gate level, generate and report DV metrics.
Typically requires at least 10+ years of industry experience.
Prior verification team management experience is required.
Prior experience verifying silicon ICs shipping in high volume is required.
Advanced knowledge of ASIC design and verification flow from RTL to test generation.
Experience with low-level programming of systems in C/C++/assembly.
Experienced with UVM. Specman is a plus.
Experienced in writing scripts in languages such as Perl, Python, and Tcl.
Understanding of constrained random verification process, functional coverage, and code coverage.
Experience with formal verification tools is a plus.
Excellent communication skills in English are required with knowledge of the German language an asset.
Contact Dave at IC Resources to apply.
Applicants with experience in the following; Semiconductor, ASIC, Analog / Mixed Signal IC, Verification, Leader, Manager, UVM, systemVerilog, Specman, Perl, Python, Tcl, scripts, test, formal, regression, coverage, DV, Location: Munich, Germany.