Senior / Principal Verification Engineer - Edinburgh
With continued business success fuelling growth in their engineering team, my client have created a number of opportunities at Senior and Principal levels for experienced IC Verification Engineers in their Development Centre in Edinburgh, UK.
Within the Digital IC Design Group, the successful applicant will assume a role as IC Verification Engineer, and drive the planning and participate in the execution of verification activities for complex IP blocks using state-of-the-art verification methodologies, in accordance with project plans.
To be successful, you will require
*Extensive industrial experience in state-of-the art verification methodologies owning and leading the verification of SoCs
*SystemVerilog for verification using advanced verification methodologies (preferably OVM/UVM or similar - Specman, e, SystemC, etc)
*Assertions based verification
*Constraint random driven verification
*Fluent in either Verilog or VHDL RTL coding and ASIC design methodology
You will be required to work to a high standard and within deadline, be self-motivated and work well in team. The ability to propose innovative and leading edge solutions will be a strong benefit.
Please contact Dave Dixon at IC Resources.
Keywords : ASIC, IP, IC, SOC, Design, Verification, Senior, Principal, Engineer, VHDL, Verilog, SystemVerilog, OVM, UVM, assertions, constraints, metric-driven, specman, SystemC, random, Edinburgh, Scotland, UK.