{"id":123047,"date":"2026-05-12T00:00:00","date_gmt":"2026-05-11T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/principal-asic-design-engineer-457361\/"},"modified":"2026-07-25T02:07:58","modified_gmt":"2026-07-25T01:07:58","slug":"principal-asic-design-engineer-457361","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/de\/jobs\/principal-asic-design-engineer-457361\/","title":{"rendered":"Principal ASIC Design Engineer"},"content":{"rendered":"<p><span style=\"font-family: Verdana;font-size: 14px\">ASIC Design Engineer &#8211; all levels<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">You must be prepared to travel into Cambridge 2-3 times per week.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">A fast-growing US start-up is expanding into the UK and building a world-class hardware team from the ground up. Backed by a proven leadership team with a strong track record of success, this is a rare opportunity to join at an early stage and play a key role in the next wave of AI innovation.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">As AI workloads become increasingly complex, the demand for high-performance compute platforms integrating CPUs, GPUs, and neural accelerators is accelerating rapidly \u2014 and this company is at the forefront of that evolution.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">They are now looking for an experienced ASIC Design Engineer to join their Fabric IP team, bringing deep expertise in microarchitecture and RTL design to help shape the future of their technology portfolio.<\/span><\/p>\n<h3><span style=\"font-family: Verdana;font-size: 14px\">What you\u2019ll be doing<\/span><\/h3>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Architect and develop microarchitectures for a suite of highly configurable IPs<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Drive RTL development with a strong focus on performance, power, and area optimisation<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Collaborate closely with verification teams on assertions, test plans, coverage, debug, and validation activities<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Contribute to the development of next-generation interconnect and compute technologies<\/span><\/li>\n<\/ul>\n<h3><span style=\"font-family: Verdana;font-size: 14px\">What they\u2019re looking for<\/span><\/h3>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">BS\/MS in Electrical Engineering, Computer Engineering, or Computer Science<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">8+ years of hands-on experience in microarchitecture and RTL development<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Strong Verilog\/SystemVerilog expertise<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Solid understanding of industry-standard EDA tools and design methodologies<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Deep knowledge of on-chip interconnects and NoCs<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Experience with cache coherency, memory subsystems, interconnects, or NoC IP is highly desirable<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Background in CPU\/GPU design would be a strong advantage<\/span><\/li>\n<\/ul>\n<h3><span style=\"font-family: Verdana;font-size: 14px\">What\u2019s on offer<\/span><\/h3>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Competitive base salary up to \u00a3120,000 depending on experience<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Share options and performance-related bonus<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Opportunity to join as one of the first UK hires<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Chance to influence both the technology and culture of a pioneering AI hardware company<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Work alongside an elite global engineering team tackling cutting-edge challenges in compute architecture<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">To be considered, you must already be living and working in the UK and be happy to work onsite in either Bristol or Cambridge.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">For more information, please contact Rachel Mason at IC Resources&nbsp;<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>ASIC Design Engineer &#8211; all levels You must be prepared to travel into Cambridge 2-3 times per week. A fast-growing US start-up is expanding into the UK and building a world-class hardware team from the ground up. Backed by a proven leadership team with a strong track record of success, this is a rare opportunity [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[692],"consultants":[408],"industry":[],"class_list":["post-123047","jobs","type-jobs","status-publish","hentry","consultants-rachel-mason"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Principal ASIC Design Engineer - England<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/ic-resources.com\/de\/jobs\/principal-asic-design-engineer-457361\/\" \/>\n<meta property=\"og:locale\" content=\"de_DE\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Principal ASIC Design Engineer - England\" \/>\n<meta property=\"og:description\" content=\"Apply to Principal ASIC Design Engineer - Bristol, England. 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