{"id":145964,"date":"2026-06-12T00:00:00","date_gmt":"2026-06-11T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/staff-digital-ic-designer-472838\/"},"modified":"2026-07-25T10:06:19","modified_gmt":"2026-07-25T09:06:19","slug":"staff-digital-ic-designer-472838","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/de\/jobs\/staff-digital-ic-designer-472838\/","title":{"rendered":"Staff Digital IC Designer"},"content":{"rendered":"<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">We are seeking a highly skilled and experienced Staff Digital Design Engineer to join our clients IC design team in Norway. This is an exciting opportunity to contribute to cutting-edge projects in the field of digital design for CMOS Image Sensors (CIS). The ideal candidate will have a strong background in ASIC design and verification, a passion for innovation, and the ability to mentor junior team members while collaborating across functional areas.<\/span><\/p>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Responsibilities<\/strong><\/span><br \/><span style=\"font-family: Verdana;font-size: 14px\">As a Staff Digital Design Engineer, your key responsibilities will include:<\/span><\/p>\n<ul style=\"margin-bottom: 0cm;margin-top: 0px\">\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Designing and verifying digital IP for CMOS Image Sensors (CIS).<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Defining chip-level architecture with a focus on power, performance, and area trade-offs, and building top-level and module specifications.<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Performing logic synthesis and collaborating with the backend team for floor planning, static timing analysis (STA), and design-for-test (DFT).<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Driving innovation and continuous improvement in the design flow.<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Mentoring and guiding junior team members.<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Participating in project planning and progress tracking to ensure timely delivery.<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Leading full-chip integration and verification efforts.<\/span><\/li>\n<li style=\"margin: 0cm 0cm 8pt 24px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Supporting silicon bring-up, validation, and debugging activities.<\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\"><strong>Qualifications<\/strong><\/span><br \/><span style=\"font-family: Verdana;font-size: 14px\">To be successful in this role, you should meet the following qualifications:<\/span><\/p>\n<ul style=\"margin-bottom: 0cm;margin-top: 0px\">\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">A minimum of a Master\u2019s degree in Electrical Engineering (MSEE) with at least 7+ years of experience in digital design.<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Expertise in RTL design and verification for ASICs.<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Proven experience in handling logic synthesis and static timing analysis across multiple projects.<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Comprehensive knowledge of the chip development cycle, including design specification, architecture definition, low-power design, tape-out, and chip validation\/debug.<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Technical leadership experience is highly desirable.<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Familiarity with ASIL, DFT, and image processing\/DSP is a plus.<\/span><\/li>\n<li style=\"margin: 0cm 0cm 0cm 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Excellent command of English as a working language.<\/span><\/li>\n<li style=\"margin: 0cm 0cm 8pt 0px;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">Strong ability to work collaboratively with cross-functional teams.<\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm 0cm 8pt;line-height: 115%;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-family: Verdana;font-size: 14px\">If you think you have the right skills and are not in Norway already, please contact Ane @ IC Resources including a cover letter outlining your motivation to relocate to Norway and your motivation to contribute to our clients\u2019 innovative projects.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>We are seeking a highly skilled and experienced Staff Digital Design Engineer to join our clients IC design team in Norway. This is an exciting opportunity to contribute to cutting-edge projects in the field of digital design for CMOS Image Sensors (CIS). The ideal candidate will have a strong background in ASIC design and verification, [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[692],"consultants":[666],"industry":[],"class_list":["post-145964","jobs","type-jobs","status-publish","hentry","consultants-ane-bauer"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Staff Digital IC Designer - Norway<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/ic-resources.com\/de\/jobs\/staff-digital-ic-designer-472838\/\" \/>\n<meta property=\"og:locale\" content=\"de_DE\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Staff Digital IC Designer - Norway\" \/>\n<meta property=\"og:description\" content=\"Apply to Staff Digital IC Designer - Oslo, Norway. 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