{"id":153579,"date":"2026-06-17T00:00:00","date_gmt":"2026-06-16T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/senior-verification-engineer-475100\/"},"modified":"2026-08-15T22:07:20","modified_gmt":"2026-08-15T21:07:20","slug":"senior-verification-engineer-475100","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/de\/jobs\/senior-verification-engineer-475100\/","title":{"rendered":"Senior Verification Engineer"},"content":{"rendered":"<p>We are seeking a highly skilled and experienced Senior Verification Engineer to join this innovative team. This role offers a unique opportunity to work on advanced verification methodologies and collaborate with a multidisciplinary team of engineers. If you are passionate about verification and thrive in a fast-paced, collaborative environment, we encourage you to apply.<\/p>\n<p>Your responsibilities as a Senior Verification Engineer will include:<\/p>\n<ul>\n<li>Developing SystemVerilog Real Number Modeling (<strong>SV-RNM)<\/strong> models for <strong>analog and mixed-signal circuits<\/strong>.<\/li>\n<li>Creating comprehensive verification plans based on chip or block specifications.<\/li>\n<li>Building <strong>UVM<\/strong>-based verification environments, including scoreboards, monitors, and sequencers.<\/li>\n<li>Conducting digital-top verification using SystemVerilog.<\/li>\n<li>Defining and implementing SystemVerilog Assertions (SVA).<\/li>\n<li>Collaborating with cross-functional teams, including design, test, and verification engineers, to ensure efficient communication and idea exchange.<\/li>\n<\/ul>\n<p>Qualifications:<\/p>\n<ul>\n<li>Master\u2019s degree 5+ years industry experience in the Functional verification in the Semiconductor industry.<\/li>\n<li>Proficiency in SystemVerilog and Object-Oriented Programming (OOP) principles.<\/li>\n<li>Expertise in UVM-based verification methodologies.<\/li>\n<li>Strong experience in writing SystemVerilog Assertions (SVA).<\/li>\n<li>Fluency in scripting languages such as Perl or Python.<\/li>\n<li>Experience generating functional models for analog blocks using SystemVerilog RNM, Wreal (V-AMS), or similar techniques.<\/li>\n<li>Familiarity with UVM-AMS methodology.<\/li>\n<\/ul>\n<p>For more information and an initial conversation please contact Ane @ IC Resources with your CV!<\/p>\n","protected":false},"excerpt":{"rendered":"<p>We are seeking a highly skilled and experienced Senior Verification Engineer to join this innovative team. This role offers a unique opportunity to work on advanced verification methodologies and collaborate with a multidisciplinary team of engineers. If you are passionate about verification and thrive in a fast-paced, collaborative environment, we encourage you to apply. Your [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[698],"consultants":[666],"industry":[],"class_list":["post-153579","jobs","type-jobs","status-publish","hentry","consultants-ane-bauer"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Senior Verification Engineer - Germany<\/title>\n<meta name=\"description\" content=\"Apply to Senior Verification Engineer - Bavaria, Germany. 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