{"id":170601,"date":"2026-07-07T00:00:00","date_gmt":"2026-07-06T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/senior-dft-engineer-482999\/"},"modified":"2026-07-25T02:06:01","modified_gmt":"2026-07-25T01:06:01","slug":"senior-dft-engineer-482999","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/de\/jobs\/senior-dft-engineer-482999\/","title":{"rendered":"Senior DFT Engineer"},"content":{"rendered":"<p><span style=\"font-family: Verdana;font-size: 14px\">We are seeking a highly skilled and motivated Senior DFT (Design for Test) Engineer to join our growing ASIC team. This is an exciting opportunity to contribute to the development of next-generation products in a dynamic and collaborative environment. Our ASIC team oversees the entire silicon flow, from specification and design to verification, implementation, ATE testing, and qualification. As part of a small, versatile team, you will have the opportunity to engage in all aspects of delivering successful products to production.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">In this role, you will be responsible for creating, implementing, and verifying DFT solutions for future ASIC designs, ensuring that quality standards are upheld for products shipping in volume. You will leverage advanced DFT methodologies to optimize test coverage, cost, and time-to-market.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\"><strong>Responsibilities:<\/strong><\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Define and implement DFT strategies at the chip, subsystem, and IP levels, balancing structural and functional methods while making pragmatic trade-offs<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Utilize Tessent DFT tool flows for inserting MBIST, EDT, SSN, scan controls via IJTAG, and IP test using ICL\/PDL in both flat and hierarchical designs<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Verify DFT structures and debug related issues to ensure robust design implementation<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Support DFT processes through implementation and sign-off, including generating timing constraints and resolving timing, power, and formal equivalence issues<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\"><strong>Qualifications:<\/strong><\/span><\/p>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">A degree in electronic engineering, computer science, or a related discipline plus at least 5 years industry experience in DFT Engineering<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Proven experience with IC development flows<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Proficiency with Tessent DFT tools<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Strong understanding of complex IP issues related to DFT, including on-chip clocking<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Hands-on experience in ATPG, MBIST, and simulation debugging, including UPF-related issues<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Proficiency in scripting, particularly TCL<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">If you are a dedicated professional with a passion for DFT engineering and a desire to contribute to cutting-edge ASIC development and want to know more about this opportunity, please contact Ane @ IC Resources with your CV and a time for an initial call. Priority will be given to application from within the UK followed by EU.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>We are seeking a highly skilled and motivated Senior DFT (Design for Test) Engineer to join our growing ASIC team. This is an exciting opportunity to contribute to the development of next-generation products in a dynamic and collaborative environment. Our ASIC team oversees the entire silicon flow, from specification and design to verification, implementation, ATE [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[718],"consultants":[801],"industry":[],"class_list":["post-170601","jobs","type-jobs","status-publish","hentry","consultants-steph-hutchinson"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Senior DFT Engineer - England<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/ic-resources.com\/de\/jobs\/senior-dft-engineer-482999\/\" \/>\n<meta property=\"og:locale\" content=\"de_DE\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Senior DFT Engineer - England\" \/>\n<meta property=\"og:description\" content=\"Apply to Senior DFT Engineer - Cambridgeshire, England. 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