{"id":201752,"date":"2026-08-19T00:00:00","date_gmt":"2026-08-18T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/senior-analog-ic-layout-engineer-503116\/"},"modified":"2026-09-02T22:07:30","modified_gmt":"2026-09-02T21:07:30","slug":"senior-analog-ic-layout-engineer-503116","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/de\/jobs\/senior-analog-ic-layout-engineer-503116\/","title":{"rendered":"Senior Analog IC Layout Engineer"},"content":{"rendered":"<p><span style=\"font-family: Verdana;font-size: 14px\">I am recruiting for a Senior Layout Engineer to join my client\u2019s semiconductor design team in the Wiltshire area.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">My client develops ICs for a range of industrial and sensing applications. The Senior Layout Engineer will play an important role in taking mixed signal designs from initial layout through physical verification and tapeout.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\"><strong>The role<\/strong><\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">The Senior Layout Engineer will be responsible for:<\/span><\/p>\n<ul type=\"disc\">\n<li><span style=\"font-family: Verdana;font-size: 14px\">Leading block and chip level layout and floorplanning<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Working closely with analog designers on layout topology, constraints and optimisation<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Managing physical verification and supporting tapeout activities<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Contributing to successful silicon releases across multiple projects<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Supporting CAD tools, PDKs and design rule verification<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Improving layout processes and methodologies<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Providing technical guidance and mentoring to other engineers<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Working with internal teams and external suppliers where required<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">The Senior Layout Engineer role would suit someone who enjoys working closely with analog design teams and wants to take ownership of technically challenging layout projects within an established semiconductor environment.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Visa sponsorship is unfortunately not available for this position, and the role requires the successful candidate to work full-time on site.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Please contact Parm Shergill for more information.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>I am recruiting for a Senior Layout Engineer to join my client\u2019s semiconductor design team in the Wiltshire area. My client develops ICs for a range of industrial and sensing applications. The Senior Layout Engineer will play an important role in taking mixed signal designs from initial layout through physical verification and tapeout. The role [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[685],"consultants":[21],"industry":[],"class_list":["post-201752","jobs","type-jobs","status-publish","hentry","consultants-parm-shergill"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v27.8) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Senior Analog IC Layout Engineer - England<\/title>\n<meta name=\"description\" content=\"Apply to Senior Analog IC Layout Engineer - Wiltshire, England. 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