{"id":221942,"date":"2026-09-17T00:00:00","date_gmt":"2026-09-16T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/senior-ic-layout-engineer-516721\/"},"modified":"2026-09-29T10:09:59","modified_gmt":"2026-09-29T09:09:59","slug":"senior-ic-layout-engineer-516721","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/de\/jobs\/senior-ic-layout-engineer-516721\/","title":{"rendered":"Senior IC Layout Engineer"},"content":{"rendered":"<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;font-family: Verdana\">This is a new opportunity for a Senior IC Layout Engineer with an innovative deep-tech company specialising in advanced semiconductor technologies, based in Oxford. Hybrid working is available with this position, with a market-topping salary + RSU package. <\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;font-family: Verdana\">&nbsp;<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;font-family: Verdana\">As our client continues to scale their processor design team, they are looking for a Senior IC Layout Engineer to play a key role in taking complex chip designs from initial requirements through to physical implementation and tape-out.<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;font-family: Verdana\">&nbsp;<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;font-family: Verdana\">This is a hands-on role suited to an experienced layout engineer who enjoys working closely with design, engineering, scientific and fabrication teams, and who is comfortable taking ownership of projects from concept through to final delivery.<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;font-family: Verdana\">&nbsp;<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;font-family: Verdana\">Responsibilities<\/span><\/p>\n<ul>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Take ownership of chip designs through the full development process, from requirements and specifications through to layout and tape-out<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Translate system and design requirements into practical chip-level physical implementations<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Design and lay out complex, multi-layer semiconductor devices, including detailed metal routing and interconnects<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Consider interfaces and compatibility between different technologies and components within the overall design<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Work closely with scientists, engineers and fabrication partners to understand requirements and resolve design constraints<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Collaborate across multiple teams to ensure designs are technically feasible and compatible with manufacturing requirements<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Identify and resolve layout and physical-design challenges throughout the development process<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Take responsibility for individual projects and drive them through to successful tape-out<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Contribute to improving layout methodologies, processes and automation within the wider design team<\/span><\/li>\n<\/ul>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;font-family: Verdana\">Requirements<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;font-family: Verdana\">We&#8217;re looking for an experienced engineer with strong hands-on IC layout experience and an understanding of the wider chip design process. You should be comfortable working across disciplines, translating requirements into physical designs and understanding how different elements of a chip interact and constrain one another.<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;font-family: Verdana\">&nbsp;<\/span><\/p>\n<p style=\"margin: 0cm;font-size: 12pt;font-family: Aptos, sans-serif\"><span style=\"font-size: 14px;font-family: Verdana\">You will ideally have experience with:<\/span><\/p>\n<ul>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Complex, multi-layer IC or semiconductor layout<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Metal routing and physical implementation<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Taking designs through to tape-out<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Cadence or equivalent IC layout tools<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Working with design rules, manufacturing constraints and physical design requirements<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Working collaboratively with scientists, engineers and fabrication teams<\/span><\/li>\n<li><span style=\"font-size: 14px;font-family: Verdana\">Taking ownership of technically complex projects and delivering them independently<\/span><\/li>\n<\/ul>\n<p><span style=\"font-size: 14px;font-family: Verdana\">For more details or to apply, get in touch with Caroline Pye.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>This is a new opportunity for a Senior IC Layout Engineer with an innovative deep-tech company specialising in advanced semiconductor technologies, based in Oxford. Hybrid working is available with this position, with a market-topping salary + RSU package. &nbsp; As our client continues to scale their processor design team, they are looking for a Senior [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709,680],"job_skillset":[685],"consultants":[344],"industry":[],"class_list":["post-221942","jobs","type-jobs","status-publish","hentry","consultants-caroline-pye"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v28.5) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Senior IC Layout Engineer - England<\/title>\n<meta name=\"description\" content=\"Apply to Senior IC Layout Engineer - Oxfordshire, England. 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