{"id":225160,"date":"2026-09-21T00:00:00","date_gmt":"2026-09-20T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/senior-verification-engineer-518609\/"},"modified":"2026-09-28T10:09:30","modified_gmt":"2026-09-28T09:09:30","slug":"senior-verification-engineer-518609","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/de\/jobs\/senior-verification-engineer-518609\/","title":{"rendered":"Senior Verification Engineer"},"content":{"rendered":"<p><span style=\"font-family: Verdana;font-size: 14px\">If verification is your thing, this is worth a look.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">I\u2019m working with a specialist European engineering company focused almost entirely on ASIC and SoC verification. They are growing their verification team and currently have multiple openings across 10+ live projects, covering everything from HPC and AI silicon to automotive, space, sensors and advanced SoCs.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">This is a strong fit for experienced engineers who want variety, technical depth and the chance to work with other people who genuinely know verification.<\/span><\/p>\n<h2><span style=\"font-family: Verdana;font-size: 14px\">What you\u2019ll work on<\/span><\/h2>\n<ul>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Complex IP and SoC verification<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">SystemVerilog \/ UVM testbench development<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Verification planning, coverage and sign-off<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">UVM VIP development<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Formal Verification and SVA<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">ARM and RISC-V based SoCs<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">AXI, AHB, APB, CHI<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">PCIe, CXL, Ethernet, Bluetooth<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">Python, C and C++ based verification environments<\/span><\/li>\n<li><span style=\"font-family: Verdana;font-size: 14px\">New methodologies including Formal and PSS<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: Verdana;font-size: 14px\">You\u2019ll also have the chance to mentor more junior engineers and contribute to improving verification flows and methodologies.<\/span><\/p>\n<h2><span style=\"font-family: Verdana;font-size: 14px\">What they\u2019re looking for<\/span><\/h2>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Ideally 5+ years of ASIC \/ SoC Design Verification experience, with strong knowledge of:<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">SystemVerilog | UVM | ASIC Verification | SoC Verification | IP Verification | Python | Formal Verification | SVA | Verification Planning | AMBA | PCIe | CXL<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">You do not need every protocol on the list. The company has a wide range of projects and is actively looking for different verification backgrounds.<\/span><\/p>\n<h2><span style=\"font-family: Verdana;font-size: 14px\">Why it\u2019s interesting<\/span><\/h2>\n<p><span style=\"font-family: Verdana;font-size: 14px\">The big attraction here is variety.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">You are not joining one product team to verify the same architecture for years. You\u2019ll work across different projects, industries and technical challenges, surrounded by engineers who specialise in verification.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">There is also a strong focus on technical development, with extensive internal training covering UVM, Formal Verification, Verification Planning, AI and advanced verification techniques.<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">Location: France or Sweden<\/span><br \/><span style=\"font-family: Verdana;font-size: 14px\">Working model: Flexible \/ remote options depending on project<\/span><br \/><span style=\"font-family: Verdana;font-size: 14px\">Eligibility: You must already have the right to work in the EU<\/span><\/p>\n<p><span style=\"font-family: Verdana;font-size: 14px\">If you\u2019re an experienced ASIC \/ SoC Verification Engineer and want to work somewhere where verification is the main event rather than an afterthought, get in touch with Steph Hutchinson for more details.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>If verification is your thing, this is worth a look. I\u2019m working with a specialist European engineering company focused almost entirely on ASIC and SoC verification. They are growing their verification team and currently have multiple openings across 10+ live projects, covering everything from HPC and AI silicon to automotive, space, sensors and advanced SoCs. [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[698],"consultants":[801],"industry":[],"class_list":["post-225160","jobs","type-jobs","status-publish","hentry","consultants-steph-hutchinson"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v28.5) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Senior Verification Engineer - France<\/title>\n<meta name=\"description\" content=\"Apply to Senior Verification Engineer - Auvergne Rhone Alpes, France. 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