{"id":225164,"date":"2026-09-22T00:00:00","date_gmt":"2026-09-21T23:00:00","guid":{"rendered":"https:\/\/ic-resources.com\/jobs\/digital-design-engineer-518678\/"},"modified":"2026-09-27T06:06:42","modified_gmt":"2026-09-27T05:06:42","slug":"digital-design-engineer-518678","status":"publish","type":"jobs","link":"https:\/\/ic-resources.com\/de\/jobs\/digital-design-engineer-518678\/","title":{"rendered":"Digital Design Engineer"},"content":{"rendered":"

Want to work on the digital architecture behind a new generation of high-bandwidth, low-power AI interconnect technology?<\/span><\/p>\n

I\u2019m working with an advanced semiconductor company developing chiplet-based connectivity and memory fabric technology for AI infrastructure, using a highly differentiated approach to moving data over copper.<\/span><\/p>\n

They are now looking for an experienced Digital IC Design Engineer to work on very high-speed digital circuits and interfaces.<\/span><\/p>\n

What you\u2019ll work on<\/span><\/strong><\/h2>\n
    \n
  • RTL design and microarchitecture for high-speed digital blocks<\/span><\/li>\n
  • Digital circuits for multi-Gigabit serial links, DDR and memory interfaces<\/span><\/li>\n
  • PCIe, USB4 and high-speed communication protocols<\/span><\/li>\n
  • Analog \/ digital interface definition alongside mixed-signal designers<\/span><\/li>\n
  • Logic synthesis, STA, CDC and lint<\/span><\/li>\n
  • IP and chip-level integration<\/span><\/li>\n
  • Verification and design sign-off<\/span><\/li>\n
  • Post-silicon bring-up, debug and characterisation<\/span><\/li>\n
  • Working closely with analog, verification and physical design teams<\/span><\/li>\n<\/ul>\n

    What they\u2019re looking for<\/span><\/strong><\/h2>\n

    Ideally 5\u201310 years of digital IC \/ ASIC design experience, with strong knowledge of:<\/span><\/p>\n

    RTL Design | SystemVerilog \/ Verilog | ASIC Design | High-Speed Digital Design | SerDes | DDR | PCIe | USB4 | CDC | STA | Synthesis | Low-Power Design<\/span><\/p>\n

    Experience with multi-Gigabit transceivers, memory interfaces, mixed-signal ICs, Python scripting or Cadence tools would be particularly valuable.<\/span><\/p>\n

    Why consider it?<\/span><\/strong><\/h2>\n

    This is not generic RTL implementation.<\/span><\/p>\n

    You\u2019ll work at the boundary between digital design, mixed-signal circuits and high-speed communications, helping turn system-level ideas into production silicon.<\/span><\/p>\n

    The technology is aimed directly at one of the biggest problems in AI hardware today: moving huge amounts of data with less power, lower latency and better scalability.<\/span><\/p>\n

    Location: Lausanne, Switzerland<\/span>
    Experience: 5\u201310+ years<\/span>
    Education: MSc \/ PhD in Electronics, Electrical Engineering, Communications or equivalent experience<\/span><\/p>\n

    If your background is in high-speed digital design, SerDes, DDR, PCIe or communications ASICs, I\u2019d be keen to speak with you contact Steph Hutchinson for more details.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"

    Want to work on the digital architecture behind a new generation of high-bandwidth, low-power AI interconnect technology? I\u2019m working with an advanced semiconductor company developing chiplet-based connectivity and memory fabric technology for AI infrastructure, using a highly differentiated approach to moving data over copper. They are now looking for an experienced Digital IC Design Engineer […]<\/p>\n","protected":false},"featured_media":0,"template":"","team-industry":[],"job_sector":[699],"job_expertise":[709],"job_skillset":[692],"consultants":[801],"industry":[],"class_list":["post-225164","jobs","type-jobs","status-publish","hentry","consultants-steph-hutchinson"],"acf":[],"yoast_head":"\nDigital Design Engineer - Switzerland<\/title>\n<meta name=\"description\" content=\"Apply to Digital Design Engineer - Lausanne, Switzerland. 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