Analog IC Layout Engineer, The Hague

Analog IC Layout Engineer, Delft

Job ID: 169420
Location: The Hague, Rotterdam, Netherlands, Europe
Salary: €40,000 and more depending on experience
Job Type: Permanent
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A Semiconductor company with a focus on Power conversion and Sensor Interfacing is looking for an Analog IC Layout engineer who can take a leading role in creating complex IC layouts.  International applicants are welcome to get in touch!
Your responsibilities will include the following:
  • Communicate with design engineers on layout trade-offs as needed to build complex analog and mixed signal block level layouts in Sub-Micron CMOS technologies
  • Deliver high quality analog block layouts that meet stringent matching, performance, area and power requirements while conforming to all PDV design requirements and meet project milestone deadlines
  • Running complete set of design verification tools available on block-level, Sub-System level, and top-level layouts
  • Provide accurate schedules for block level, top-level layout and integration and report to layout manager
  • Recognise failure prone circuit and layout structures and propose mitigating actions
  • Debug and drive resolutions to Physical Design Kit issues, DRC/LVS/ERC improvements with respect to layouts
  • Solve problems while using a combination of technical skills, intuition, and creativity
  • Contribute ideas for improved productivity and automation of layout tasks
  • Recognise apparent mistakes in the analog design
  • Propose design changes when it benefits the layout
The successful Analog IC Layout Engineer has the following qualifications and skills:
  • BSc or MSc degree Electrical engineering, specialised in Micro-electronics
  • 3+ years’ experience creating custom analog/mixed-signal layouts at chip, block, and device levels in sub-micron CMOS technologies
  • Expertise with Cadence Virtuoso XL schematic driven layout design flow, Virtuoso Floor Planning, Constraint Driven Layout, and extraction flows
  • Expertise using Cadence verification suite (PVS-DRC, LVS, ERC); high proficiency with interpretation, debug, and understanding of results
  • Strong experience with high performance analog layout techniques for device matching, common centroid layout, isolation, shielding, use of dummy devices, parasitic sensitivities, and also chip level electromigration, IR drop, self-heating, cross coupling capacitance and DFM practices
  • Good understanding of package needs and constraints with respect to chip level
  • Layout experience with analog on-top and digital on-top flows, including defining, directing, and reviewing layout team’s work
  • Proven capability at chip and block level in floor planning, power routing, ESD, physical design area estimates, effort/schedule estimations
  • Understanding of multiple voltage (HV) domains and layout techniques required
  • Custom analog layout experience should include various analog IP blocks: PLLs, OSC, ADC, DAC, LDO and Bandgap reference
  • Excellent communication skills and ability to work with cross-functional teams in a demanding team-oriented environment
  • Self-starter and self-sufficient in problem solving and accomplishing tasks
  • Experience with Analog design is highly appreciated
  • Scripting experience in PERL or SKILL CODE is considered a plus, but not required
For more information and to apply, please click APPLY NOW to speak to a member of the team.

+44 (0)118 988 1150

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