DFT Engineer
Berkshire, England
Permanent
Excellent salary
V-182058
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Lucy Edmondson
ASIC | Verification | DFT
DFT Engineer - Join a leading Design Service Company - Exciting projects! - Reading
An innovative Design Service Company are looking for a DFT Engineer to join their team in Reading. Located in the Thames Valley, you will be based in a beautiful, scenic landscape, within a short train journey of London - so there is plenty to do outside of work whether you like countryside living or city life. The Thames Valley is also home to a number of great universities and schools, so a fantastic location for families with children.
As a leading fabless design house, my client play a key involvement in projects in the forefront of semiconductor technology. Joining them will mean a fast-paced and varied project style work.
In this role you will work within a close-knit silicon design team, and play a key role in all DFT activities.
The key skills needed for the Senior DFT Engineer are:
An innovative Design Service Company are looking for a DFT Engineer to join their team in Reading. Located in the Thames Valley, you will be based in a beautiful, scenic landscape, within a short train journey of London - so there is plenty to do outside of work whether you like countryside living or city life. The Thames Valley is also home to a number of great universities and schools, so a fantastic location for families with children.
As a leading fabless design house, my client play a key involvement in projects in the forefront of semiconductor technology. Joining them will mean a fast-paced and varied project style work.
In this role you will work within a close-knit silicon design team, and play a key role in all DFT activities.
The key skills needed for the Senior DFT Engineer are:
- A strong track record in DFT gained across several successful ASIC projects.
- Implementing DFT infrastructure.
- Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, and MBIST.
- VHDL/Verilog coding skills.
- Experience of RTL and gate-level simulation as applied to DFT verification.
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