Digital IC Verification Engineer (UVM), France

Digital IC Verification Engineer (UVM), Aix En Provence

Job ID: 182719-1
Location: France, Europe
Salary: Attractive salary and benefits - dependent on experience
Job Type: Permanent

I am looking for a Mid-level or Senior Verification engineer to join my client based in the beautiful Provence-Alpes-Côte d'Azur region of southern France.  

My client are a global leader in data & security, developer and licensor of Semiconductor IP and this growing team specialise in high-speed connectivity and protocols such as PCI Express. 

You will join the R&D team, working for the Director of Engineering and Verification Manager, where you will have responsibilities that include:
  • Define and implement verification plans and test plans to ensure the designs meet quality and performance goals
  • Build and maintain automated verification environments
  • Provide comprehensive documentation for the usage and the architecture of the verification environments as well as reports for the verification results
Skills Requirement
  • 3 + years in Design Verification
  • Experience in Verilog, System Verilog
  • Verification EDA tools, Verification methodologies, Verification IPs
  • Proficiency in programming and/or scripting languages (Python, Tcl, Perl, Cshel)
  • Background in digital circuitry or hardware logic design
  • High performance computing system, processor, cache coherency, chipset and ASICs
  • High speed interface protocols like PCIe, CCIX, CXL (advantage)
  • High performance memory interfaces (advantage)
  • Knowledge on High Speed Serdes and PHY PMA (advantage)
*Visa sponsorship can be offered if required*

For any queries please contact Rob Hudson – Senior Digital ASIC Design Recruitment Consultant

+44 (0)118 988 1150

Book a call