FPGA/ASIC Digital Design Engineer, Sophia Antipolis

FPGA/ASIC Digital Design Engineer, Paris

Job ID: 169484
Location: Sophia Antipolis, Paris, Île-de-France, France, Europe
Salary: Salary ranging from €55,000- €70,000
Job Type: Permanent
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This is an exciting opportunity for a Senior Digital Design Engineer to join my client in Paris or Sophia Antipolis. 

Working with an established client in either Sophia or Paris, you will get the opportunity to be involved in the architecture definition, design and validation of the DSP. You will join a dynamic design team and be instrumental in the design, architecture definition and verification of ASIC sub blocks. 

I am seeking several motivated digital design engineers with RTL design and verification. This role requires the successful candidate to have a solid background in digital electronic and signal processing as well as solid knowledge of digital hardware description languages VHDL or Verilog and scripting languages including Perl, TCL or Python. 

The successful Digital Design Engineer will spend time working on the specifications and definition of the Micro-architecture of digital sub blocks alongside RTL deign and should be able to elaborate detailed verification plans corresponding to circuit definitions, so experience in UVM methodology would be advantageous. 

In Sophia Antiplois our client has just built a brand new ASIC Design Centre so you will get the opportunity to work on their brand new equipment.

This role requires you to be a European Citizen as my client cannot offer visa sponsorship. 

Please do not apply if you are a graduate engineer.

For further information please contact Andrew Emberson. 


+44 (0)118 988 1150

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