An opportunity has become available for a Lead Digital Validation Engineer to join a leading semiconductor company based in the South of France.
As a Lead Digital Validation Engineer you will have a number of responsibilities that include;
- Define validation strategies and test plans
- Mentor and lead the validation team
- Debug and failure analysis of silicon issues (hands on and theoretical)
- Implement test plans on pre and post silicon platforms/environments
- Maintain and create automation scripts/flows
To be considered for the Lead Digital Validation Engineer vacancy you must have prior experience of SoC validation, project/team lead experience in a validation role, strong system level understanding of CPU/SoC architecture/memory and good hands-on lab experience. You must also have strong scripting and programming language in C++/C and PERL/Python.
You must be able to speak fluent English. French is an advantage.
If you have interest in applying to the Lead Digital Validation Engineer vacancy or would like further information, please contact Roberta Wright.