Physical Design / Implementation Engineer
Grenoble, Auvergne Rhône Alpes
Permanent
Great salary, lovely location, plus benefits.
V-169901
This job has now closed, click here to view similar opportunities
Rob Hudson
ASIC | Verification
Fantastic new opportunity as Design / Verification Engineer to work for a rapidly growing ASIC design and supply services company, based in the beautiful foothills of the French Alps.
You will be working with an established team of digital designers on exciting mixed ASIC projects, for a variety of applications and industries.
Responsibilities
As part of an ASIC/SoC design team, you will be working with analog/digital design teams on end to end duties for physical implementation: synthesis, DfT, floorplan, clock tree synthesis, place & route and verification's (STA, consumption analysis, thermal analysis, proof of equivalence, DRC, LVS, IR- Drop).
Required skills
You will be working with an established team of digital designers on exciting mixed ASIC projects, for a variety of applications and industries.
Responsibilities
As part of an ASIC/SoC design team, you will be working with analog/digital design teams on end to end duties for physical implementation: synthesis, DfT, floorplan, clock tree synthesis, place & route and verification's (STA, consumption analysis, thermal analysis, proof of equivalence, DRC, LVS, IR- Drop).
Required skills
- Strong knowledge of RTL - GDSII
- Understanding of DFT requirements
- Timing / STA, RTL code, basic circuit architecture
- Set up environments and synthesis / DfT / Place & Route flows to release low voltage and low power implementations
- ISO9001 / ISO13485 / EN9100 standards
- Engineering degree (or similar) in microelectronics
- 5 years’+ experience in physical implementation (DfT or place & route + STA ) with: ability to set up a flow for a circuit of a certain complexity or in a new environment, knowledge of several technologies from 180nm down to 22FDX (and more advanced is a plus), autonomy in TCL scripts (e.g. Python), ability to write timing constraints, UPF / CPF files.
- Fluent English / Fluent French is a bonus!
- Confident skills in one of the following;
- P&R tool (ICC2 – Synopsys, Innovus-Cadence)
- static timing analysis (PrimeTime)
- logical synthesis (Design Compiler)
- DfT (Tessent)
- logic or analog or mixed simulation for electrical simulations
- IR-Drop analysis
Related roles
Search all our jobsDigital Verification Engineer - UVM
Grenoble, Auvergne Rhône Alpes
Permanent
€ depending on years of experience
Read more
Senior UVM Verification Engineer
Grenoble, Auvergne Rhône Alpes
Permanent
€ depending on technical knowledge and years of experience
Read more
Senior Digital Design Engineer (ASIC / NOC / SOC)
Paris, Île-de-France,
Sophia Antipolis, France
Permanent
€50-80k (depending on experience)
Read more