Job ID: 176657
Location: Wiltshire, Surrey, Oxfordshire, Berkshire, England, UK
Salary: Competitive salary and bonus
Job Type: Permanent
Physical Design Lead – Thames Valley
I am looking for Physical Design Engineers of all levels to come and join my client, a leading IC design service company who work within a range of markets such as automotive, healthcare, industrial and consumer markets. This is a fantastic opportunity to join a growing team where no day will ever be the same giving you the opportunity to work on range of different projects. This role would best suit an Engineer who is always interested in taking on new challenges and looking to build up a range of skills.
Responsibilities would include:
- Take full-flow ownership of all stages of the digital RTL-to-GDSII implementation flow for complex block-level or full-chip ASIC designs.
- Work closely with customers and other teams to deliver projects on-time and to the required performance and quality levels.
- Setup, run, and maintain EDA tool flows, as needed, for each stage of the development flow.
- Keep up to date with all aspects of advanced ASIC implementation methodology
- Hands-on experience with either Synopsys ICC1/2 or Cadence Innovus for block-level and/or full-chip physical design, preferably down to ~7nm FF.
- RTL synthesis using Design Compiler or Genus, including DFT/scan-insertion.
- Power-management implementation using UPF/CPF, including verification and power estimation.
- Timing closure and STA, including constraint development and verification.
- IR-drop/EM modelling, analysis, and verification.
- Setup, use, and verification of RC extraction flows.
- Ability to setup, run, and debug DRC/LVS/ERC/DFM using at least one of the main EDA tool sets.
For more information on this role or others then please contact Jordan Browne.