This is a new Senior Digital Verification Engineer opportunity with a hugely successful Semiconductor company based in Munich.
Our client is a long-established, highly innovative IC company whose technology equips millions of automotive products around the world. They are now seeking a Senior Digital Verification Engineer to join them working on latest high-speed interconnect ASICs. If you are looking for a long-term, stable position within a steadily growing Semiconductor company, this is a great option.
The Senior Digital Verification Engineer will join our client’s expanding Digital ASIC team and take responsibility for:
- Enhancing the UVM system level verification environment
- Defining and implementing module level verification environments
- Working closely with the ASIC design team to generate verification plans
- Constrained random and assertion-based verification
Requirements:
- A Degree in Computer Science / Electronics Engineering or related field
- Fluent language skills in English, and at least intermediate level German
- A number of years’ experience in digital ASIC Verification (SystemVerilog / UVM)
- Scripting skills in Python would be a plus
Get in touch today: contact Caroline Pye @ IC Resources for details.
