Senior (Principal) Mixed Signal Verification Engineer, Munich

Senior (Principal) Mixed Signal Verification Engineer, Munich

Job ID: 180419
Location: Munich, Bavaria, Germany, Europe
Salary: Depending on experience
Job Type: Permanent

A successful semiconductor company in the Munich is looking for a Senior (Principal) Mixed Signal Verification Engineer. The role offers scope to drive Mixed Signal Methodology Europe wide.

Your responsibilities will be to guarantee specification compliance of the mixed signal design by means of advanced verification methodologies and concepts.
  • Support the definition and enhancement of state-of-the-art methodologies serving as clear verification sign-off criteria for tape out.
  • Verification planning, maintenance, feature extraction, verification test case and checker development for AMS and DMS verification at chip and block level
  • Develop behavioural models of analog blocks for DMS. Improve modelling and model validation techniques.
  • Develop verification strategy for mixed signal IPs and implement the verification IP following object-oriented programming principles and methodologies including UVM (for DMS) or relevant state of the art AMS verification methodologies
  • Initiate and participate in review meetings with Design and Verification engineers
  • Lead mixed signal verification of PMICs or sub-systems.
  • Interaction and presentation to internal and customer reviews.
  • Mentor junior engineers in the team.
  • Bridge the gap between analog and digital verification
  • Deliver verification work in the agreed time scales as set by program schedule for all assigned tasks.
  • Document and log all verification work
  • Verification strategy and concept in place in an early phase of the project
  • Ensured specification compliance by having required verification metrics in place
  • Verification concept and approaches according to corporate rules and guidelines
  • Close collaboration together with other AMS and DMS experts in the Company
The successful Senior (Principal) Mixed Signal Verification Engineer has the following qualifications and skills:
  • Engineering degree (Masters/PhD) plus at leasy7 years in advanced verification methodologies, owning the verification of complex mixed signal designs.
  • SystemVerilog for verification using advanced verification methodologies preferably UVM.
  • Assertion based and constrained random verification.
  • Behavioural modelling of analog blocks in SystemVerilog and/or Verilog-AMS.
  • Familiarity with analog mixed signal verification (AMS), analog design and digital design
 For more information about the team, company and the role - contact Ane with your CV and a time for an initial conversation about your expectations.



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