Verification Engineer
Bristol, Cambridgeshire, England
Permanent
Great compensation package
V-177725
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Rachel Mason
ASIC | Verification
NEW VERIFICATION ENGINEER – Bristol OR Cambridge
X 2 Positions – Mid-level and Senior
This is a superb opportunity to join a leading provider of solutions for the design, simulation and manufacture of products across many different industries. Formula 1 cars, skyscrapers, ships, space exploration vehicles!
To be located in one of the biggest technology hubs in the UK – Bristol or Cambridge. Both fantastic UK cities.
I am looking for highly capable and dedicated Verification Engineer to join their growing team. You will have the opportunity to enjoy shaping the development of ground-breaking silicon IP.
I am looking for highly capable and dedicated engineers with a micro-electronics background to join my clients growing team. You will have the opportunity to enjoy shaping the development of ground-breaking silicon IP. You will become responsible for;
X 2 Positions – Mid-level and Senior
This is a superb opportunity to join a leading provider of solutions for the design, simulation and manufacture of products across many different industries. Formula 1 cars, skyscrapers, ships, space exploration vehicles!
To be located in one of the biggest technology hubs in the UK – Bristol or Cambridge. Both fantastic UK cities.
I am looking for highly capable and dedicated Verification Engineer to join their growing team. You will have the opportunity to enjoy shaping the development of ground-breaking silicon IP.
I am looking for highly capable and dedicated engineers with a micro-electronics background to join my clients growing team. You will have the opportunity to enjoy shaping the development of ground-breaking silicon IP. You will become responsible for;
- Developing, improving and maintaining leading edge UVM verification environments for silicon IP blocks with a focus on surpassing customer expectations
- Contributing to the evolution and continuous improvement of their development processes
- Ensuring the overall quality of the released product
- 2-5 years at mid-level, Senior is 5 to10 years in verifying IP using constrained randomisation
- Experience with using SystemVerilog and UVM
- Some awareness of digital design fundamentals
- Experience with formal verification
- Experience with object-oriented software development