Analog Layout Engineer

An innovative leader in  high-speed, energy efficient, chip-to-chip link solutions is looking for a Analog Layout Engineer! Based in Lausanne you will be part of a passionate team of accomplished professionals keen to make their mark within the semiconductor industry.

In your role as Analog IC Layout Engineer you will have the following responsibilities:

• Layout and verification of analog circuits, cells, blocks and IP for multi- Gigabit high speed chip to chip communication links (SerDes up to and beyond 28Gb/s and/or memory IO) in advanced semiconductor technology nodes
• Layout and verification of very high-speed analog circuits
• Interact closely with the design team to understand requirements and implement solutions
• Support IP and chip level integration
• Support and interact with customers on requirements, and IP delivery
• Exposure to flip-chip package technologies

Experience of the Analog Layout Engineer:

• Experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuits.
• Expertise in layout of high-speed/frequency circuits like amplifiers, oscillators, phase- locked loops, delay-locked loops, and other fundamental building blocks like biasing, buffers, regulators, filters, data converters, etc.
• Understanding of layout approaches and techniques for high speed circuits, matching constraints, minimisation of parasitics, power grids and ESD requirements
• Understanding of Layout Dependent Effects and their effect • Ideally with experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm
• User of EDA tool for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM and IR drop, ESD, etc.

For more information and to apply, to the Analog Layout Engineer Position, please contact Molly