Cache Coherency Architect

San Francisco, California


Excellent salary + benefits


This is a key requirement for a Cache Coherency Architect to join our world-leading system IP client based in California.

Our client is revolutionising autonomous driving, 5G mobiles and AI. They are expanding globally, and seek a Cache Coherency Architect to undertake a critical role in optimising cache coherency solutions within the company’s advanced IP portfolio. Working closely with the hardware and software teams, the Cache Coherency Architect will develop cutting-edge cache coherent interconnect IP and ensure smooth integration with other interconnects and system IP to enable efficient communication between multiple processor and accelerator cores.

This is a highly influential role in which the Cache Coherency Architect will make a unique contribution to the creation of state-of-the-art semiconductor solutions.

The Cache Coherency Architect will have:
  • Proven experience as a Digital Chip Architect or Digital Design Engineer, with a focus on NoC (Network-on-Chip) IP development
  • An understanding of cache coherency protocols and memory hierarchy
  • An in-depth understanding of VHDL / Verilog and SoC design

For details or to apply, please contact Caroline Pye.
Apply now