Circuit Design Manager

South Holland, Netherlands


Salary dependent on experience


This job has now closed, click here to view similar opportunities
profile photo
Parm Shergill

Analog | Mixed Signal | RFIC Design - EU

The Senior Manager of Circuit Design Engineering will play a pivotal role in assembling and guiding the Delft team to create a diverse range of cutting-edge semiconductor products.

I am seeking an individual who is exceptionally driven, a self-starter, and a proficient leader, capable of steering dynamic design engineering teams.

The ideal candidate will possess superb technical acumen, managerial finesse, and exceptional communication skills. This position offers substantial exposure and significant opportunities for career advancement.

Key Responsibilities:
  • Team Building: Recruit, assemble, and inspire top-tier engineering teams.
  • Team Leadership: Lead a multifaceted IC Design team, encompassing Analog, Mixed-Signal, Digital, and Layout engineers, to develop precision timing solutions for high-performance and ultra-low power applications.
  • Technical Expertise: Provide broad and incisive technical expertise, swiftly grasp new and unfamiliar technical domains, and formulate strategies to surmount challenges or seize new opportunities.
  • Optimisation: Identify deficiencies and constraints in products and processes. Propose and implement optimised procedures suitable for the company's stage and resources.
  • Decision-Making: Make product-level decisions, encompassing aspects such as testability, manufacturing, cost, applications, and product support features.
  • Collaboration: Collaborate with Systems Engineering, Test Engineering, and Applications teams to design chips with Design for Test (DFT) and Design for Manufacturing (DFM), achieving swift silicon validation and accelerated time-to-production release.
  • Customer Engagement: Partner with Customers, Marketing, and Sales to define product strategies, roadmaps, and schedules to target and secure key design wins.
  • Project Management: Oversee engineers to achieve customer satisfaction, meet project schedules, and adhere to budget constraints.
  • Flexibility: Undertake additional projects as required by management or in response to evolving business needs.
Qualifications & Requirements:
  • Education: An MS Degree in Electrical Engineering or a related field, with a preference for a Ph.D.
  • Experience: Minimum of 10 years of industry experience in custom Analog IC circuit design, including expertise in Frequency synthesis architecture/circuits, Voltage References, bias circuits, Switched capacitor or sampling circuits, high-performance ADCs and DACs, and Linear regulators.
  • Leadership: At least 5 years of proven experience in a similar leadership role.
  • Track Record: A proven track record of designing and successfully producing complex mixed-signal chips at high volume.
  • End-to-End Expertise: Demonstrated experience in the entire product development cycle, from Product Concept through Design Implementation, Tape-out, Sampling, and production release.
  • Technical Competence: A track record in architectural development, specification writing at both system and block levels, design partitioning for noise/power/area budgeting, detailed design and simulation of analog building blocks, as well as high-speed op amps and band gaps.
  • Technical Knowledge: Proficiency in ultra-low phase-noise design, power supply noise considerations, device matching, parasitic extraction, signal integrity, and ESD.
  • Supervision: Experience in overseeing layout and editing critical blocks, as well as chip-level design and verification of complex mixed-signal chips.
  • Product Understanding: The ability to align technical, marketing, productisation, and operational aspects to optimise product development.
  • Team Building: Prior experience in recruiting, building, and leading successful teams, with a proven track record of cultivating high-performing teams.
  • Flexibility: Willingness and ability to travel both domestically and internationally.