Design Verification Engineer
Madrid, Community of Madrid
Permanent
Competitive Base + Bonus
V-200343-1
Meg Evans
ASIC | Verification
Verification Engineer
Competitive Salary + Benefits Location: Madrid (100% remote roles are available for EU Nationals)
We are working with an innovative company who is seeking a skilled Verification Engineer to join their team. This is a fantastic opportunity for a Verification Engineer who is eager to contribute to the verification of custom and standard Digital IP components in complex systems like SoCs and microprocessor cores.
Why This Opportunity?
This Verification Engineer role offers the chance to be part of an exciting environment where you would work with both custom and industry-standard components, pushing the boundaries of digital system verification. You’ll play a key role in shaping the verification strategies for high-profile projects, collaborating with design and test teams to ensure the highest quality standards.
The Role: As a Verification Engineer, your day-to-day responsibilities will include:
What We’re Looking For: To succeed in this Verification Engineer role, you should have:
How to Apply:
If you're ready to take on an exciting challenge as a Verification Engineer, I’d love to hear from you! Please get in touch to discuss this role or other opportunities we have available.
Apply now
Competitive Salary + Benefits Location: Madrid (100% remote roles are available for EU Nationals)
We are working with an innovative company who is seeking a skilled Verification Engineer to join their team. This is a fantastic opportunity for a Verification Engineer who is eager to contribute to the verification of custom and standard Digital IP components in complex systems like SoCs and microprocessor cores.
Why This Opportunity?
This Verification Engineer role offers the chance to be part of an exciting environment where you would work with both custom and industry-standard components, pushing the boundaries of digital system verification. You’ll play a key role in shaping the verification strategies for high-profile projects, collaborating with design and test teams to ensure the highest quality standards.
The Role: As a Verification Engineer, your day-to-day responsibilities will include:
- Verifying digital logic using SystemVerilog and reusable, standardised methodologies.
- Verifying systems with custom and standard IP components, including microprocessor cores and memory subsystems.
- Contributing to chip-level verification and modeling efforts.
- Working with design and test teams to define test specifications, verification plans, and transfer processes.
- Developing and maintaining verification infrastructure and tools.
What We’re Looking For: To succeed in this Verification Engineer role, you should have:
- MSc in Electronic, Electrical, Computer Engineering, or a related field.
- Experience in digital design verification tasks.
- Strong experience with Verilog, SystemVerilog, SVA, functional coverage, and scripting languages like Perl or Python.
- Familiarity with industry-standard simulators, revision control systems, and regression systems.
- UVM experience is a MUST.
- Experience with low-power techniques and the UPF flow.
- Knowledge of SoC interfaces (e.g., AHB, APB) and memory system architectures.
- A proactive, problem-solving attitude with a focus on technical excellence and zero bug tolerance.
How to Apply:
If you're ready to take on an exciting challenge as a Verification Engineer, I’d love to hear from you! Please get in touch to discuss this role or other opportunities we have available.
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