
Design Verification Engineer
San Francisco, California,
Denver, Colorado,
Ohio, Oregon, USA
Permanent
Competitive compensation package + benefits & hybrid / remote work
V-259300

Rachel Mason
ASIC | Verification
Design Verification Engineer Locations: Ohio, California, Oregon, Colorado – Hybrid/Remote Options Available
I am seeking a skilled and driven Design Verification Engineer to join a high-growth technology company born from a world-renowned security and computing R&D organization. This team is developing cutting-edge microelectronic products that enable the secure collection, processing, and distribution of critical data.
As part of a collaborative and forward-thinking engineering group, you’ll contribute to the verification of complex System-on-Chip (SoC) designs that are central to the company's mission.
Key Responsibilities
This is an opportunity to join a company at the forefront of secure microelectronics and to have a meaningful impact in a growing team. If you're ready to take on complex challenges and shape the future of SoC design, I would love to hear from you.
Please Note: You must already be based in the USA.
Apply now
I am seeking a skilled and driven Design Verification Engineer to join a high-growth technology company born from a world-renowned security and computing R&D organization. This team is developing cutting-edge microelectronic products that enable the secure collection, processing, and distribution of critical data.
As part of a collaborative and forward-thinking engineering group, you’ll contribute to the verification of complex System-on-Chip (SoC) designs that are central to the company's mission.
Key Responsibilities
- Lead functional verification of advanced SoC architectures using SystemVerilog and the Universal Verification Methodology (UVM)
- Develop detailed test plans, build reusable UVM testbenches, write test cases, and work closely with RTL designers to identify and resolve bugs
- Perform gate-level simulations and analyze process corner failures to ensure robust performance and reliability
- Utilize industry-standard tools such as Synopsys VCS, Verdi, and Spyglass to carry out verification activities
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field
- Minimum of 5 years of hands-on SoC verification experience using UVM
- Proficient in SystemVerilog and experienced in debugging RTL
- Solid understanding of ASIC development flow and digital design principles
- Scripting and programming experience in C, C++, Python, or Perl
- Experience verifying RISC-V architectures
- Familiarity with high-speed interfaces such as PCIe and DDR
- Exposure to formal verification methodologies, emulation, or FPGA prototyping
- Experience with version control (e.g., Git) and CI/CD pipelines
- Knowledge of the Chisel hardware description language
- Competitive compensation package
- Employer-paid healthcare and contributions to a Health Savings Account
- Flexible time off policy
- Hybrid and remote work options
- A fast-paced, innovative environment that values expertise, collaboration, and autonomy
This is an opportunity to join a company at the forefront of secure microelectronics and to have a meaningful impact in a growing team. If you're ready to take on complex challenges and shape the future of SoC design, I would love to hear from you.
Please Note: You must already be based in the USA.

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