Design Verification Engineer

CAMBRIDGE OPPORTUNITY - VERIFICATION ENGINEER (Mid-level through to Senior)

Due to growth, I am looking for a Verification Engineer to join an established ASIC team.

The Verification Engineer and the wider team will develop chips which are designed, verified, and implemented in-house. The work of the ASIC team includes Architecture, tradeoffs with software/hardware, RTL design, IP selection and integration, Verification at block and system level and Implementation including DFT, Synthesis, Place and Route, Timing closure and Signoff checks.

As a company they manufacture low-cost PCs, embedded systems, and microcontrollers, as well as accessories for these core products. They have sold millions since they started production over 10 years ago.

The successful Digital IC Verification Engineer will join an innovative team. You will have a good level of autonomy for IP verification planning and execution, and will be constantly interacting with the design team, composing detailed verification plans and creating test benches from scratch. You will develop automated UVM or similar test environments for block-level or chip-level verification.

This role requires a good level of experience and a wide range of skills:

• Hands-on experience with at least three projects
• Experience of creating test benches from scratch
• Good understanding of creating/integrating UVM UVCs
• Ability to write functional coverage
• Knowledge of SVA

The following would also be useful:

• Experience of Cadence simulation tool flow
• IP protocol experience, e.g. PCIe, USB, bus architectures
• Scripting languages
• Good understanding of design/front-end processes

As a city-based company you can expect a good salary and compensation package – for more information and an informal confidential chat about the role, company and your experience contact Rachel Mason.