Design Verification Lead

Verification Engineer – Senior and Principal level

Bristol, UK

This is a fantastic opportunity to help support the build of a new Bristol based Chip Team, working on innovative, class leading silicon.

My client has opened a small design centre in the bustling City of Bristol. The HQ is in the North. My client is developing a novel photonic-electronic architecture that will bring fully homomorphic encryption to the world. The development provides a huge opportunity to become the ubiquitous choice for this new upcoming market across multiple industry sectors.

In order to achieve their goal of bringing this technology to the mass market, they are assembling a highly skilled team to build a complex SoC.

I am looking for somebody to take the role of Principal Verification Engineer, although there is some scope to hire at Senior level too. You would be overall accountable for defining the verification and validation strategy for the SoC. Working with the SoC Architect and Design/Technical Lead, you would help define and execute the strategy to build a SoC that achieves our technical and commercial goals. 

You will be overall accountable for defining the verification strategy and execution, including:

• Creating and maintaining a verification/validation plan from block level to system level
• Defining the overall strategy to prove the design is functionally correct including overall methodology and execution strategy
• Defining and managing resourcing requirements to ensure on-time completion
• Defining and implementing verification metrics to monitor progress and completion
• Providing engineering leadership across the teams and working with other SoC leads to manage the delivery of the SoC

To be successful for this role you must have a strong background in SoC verification and validation.

You will have:

• A proven track record in SoC verification and validation with exposure to all phases in the flow – requirements collection, methodology and test plans, testbench implementation, coverage closure, documentation etc.
• Deep understanding of modern verification and validation techniques including formal, UVM/OVM/eRM, low power, emulation
• A strong analytical approach capable of building and using data driven approaches to reporting, closure and sign-off
• Good knowledge of the SoC design flow from specification to silicon tape-out
• The ability to communicate clearly with both expert and non-expert audiences

For more information and a chat about this superb opportunity, please contact Rachel Mason.