SW, Formal and Functional Verification Engineers can be considered
This is a fantastic opportunity to join a seed-stage start-up making a huge leap forward in general purpose computing performance and security. My clients novel processor technology will accelerate and secure Python and other managed language software. They are developing a modified RISC-V processor and an associated SW stack.
If you want to be part of an early stage start-up who are fresh from closing seed investment and rapidly starting their clean sheet design this could be for you!
Along with the founders of this unique business I am looking for bright and enthusiastic engineers, with the aim to grow steadily and hire 15 Engineers in the next 12-18 months. As one of the first Engineers into the business you will get to work in a fast paced environment, take ownership of tasks, be involved in recruitment and form development plans!
You will be the primary Verification Engineer of a RISC-V based processor core that integrates my clients novel memory management technology. There is also option to eb the Lead Engineer (depending on experience)
You will be responsible for leading the Verification of their clean sheet RISC-V processor and building upon existing Formal Verification of their memory management technology.
- 5+ years of HW Engineering experience – 3+ years in Verification
- Recent experience of tapeout at 20nm or smaller.
- Comfortable setting up new development flows and configuring associated tools from scratch.
- Comfortable contributing to functional simulator software.
- Experience using Python for HW Verification.
- Understanding of Formal Verification (nice to have)
- Experience with version control systems (Git)
If you would like to hear more information about this exciting proposition please contact Rachel Mason.
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