Digital Verifiction Engineer

Cork, Ireland


Base + RSUs + bonus scheme and relocation package


Digital Verification Engineer – World Class Semiconductor company is hiring!


I am seeking a Digital Verification Engineer to join my world-class Semiconductor client based in Southern Ireland.

This challenging position offers the Digital Verification Engineer the opportunity to work with leading edge sensor technologies embedded in smartphones, automotive, IOT, smartwatches as well as other consumer electronics devices. Job activities span the ASIC design verification process from test planning, environment development using UVM, regressions, coverage analysis and meeting all company quality metrics for tapeout.

This friendly Irish location offers an ideal mix of vibrant city life close to peaceful countryside and sweeping coastlines. There is something for everyone, with excellent amenities for families, many cultural events and festivals throughout the year, and a great culinary and music scene.

The position is technology focused and involves participation in a broad range of sensors systems engineering activities within the Sensors Technologies group. In this role, responsibilities will include:  
  • Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification
  • Developing Testbenches and Verification Components such as UVCs, C models,  and Vertical/Horizontal re-usable Verification Environments.
  • Verifying sensor algorithms RTL for ASIC tapeout quality delivery
  • Test plan development based on Design documents and interaction with design/systems engineers
  • Implementing C model integration within UVM framework.
  • Writing SystemVerilog assertions
  • Analysing coverage data and working with Design teams to address coverage holes
A very competitive basic salary, together with bonus, stock, and a generous benefits scheme including a good pension package and medical insurance. My client will provide relocation assistance to help you move and settle in.  

For this Verification role you will need:
  • ASIC design verification, UVM-based functional verification, or related work experience.
  • Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology
  • Experienced with Assertions like System Verilog Assertions
  • Experience with debugging test failures and report verification result
  • UVM,  System Verilog, Perl/Python shell-scripting skills required
  • Familiarity with C/C++
Enquire today for immediate consideration: email Rachel Mason.
Apply now