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DRC + LVS Layout Contractor

Romania, Europe

Contract

Hourly rate is dependant on location and experience

V-192899

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IC Resources is working with a Romanian client who is searching for an Analog Layout engineer with experience working on DRC and LVS. 

The client is looking for engineers within a European Timezone (+/-2hours). 

Requirments: 
  • Expert knowledge of Semiconductor process manufacturing in planar, FinFET, FD-SOI technologies, including Front-end & Back-end features, devices, layout rules, and mask creation.
  • Expert knowledge of DRC rules writing and customisation of DRC & LVS rundecks in Calibre, ICV or PVS;
  • Proven sign-off and tape-out experience in at least one of the following nodes: FinFET 16nm, FinFET 14nm, FinFET 12nm, FinFET 7nm, FinFET 5nm, FD-SOI 22nm, FD-SOI 18nm.
  • Expert knowledge of Physical Design Verification, layouting, floorplanning, constraint-driven placement, routing, power distribution, in low-power, HV and HF planar, FinFET and FD-SOI technologies;
  • Expert knowledge of DRC, LVS, Extraction, ERC, Dummy Fill, Antennas, with a plus for 3Dstack, Interposer, InFo
Working on: 
  • Working knowledge of at least one of the SVRF, TVF, OpenDFM.
  • Working knowledge of Python and TCL;
  • Working knowledge of Cadence Virtuoso Layout Suite and Siemens Calibre;
6 month contract 

Location: Remote working (with ramp up period on site) 

If the role is of interest or you would like more information, please get in touch with Imogen Hunter