Formal Verification Engineer

Job Title: Formal Verification Engineer About the Role: I am seeking a highly motivated and detail-oriented Formal Verification Engineer to join an established Verification group in the historic City of Oxford. In this role, you will be responsible for applying formal methods to verify the correctness of complex digital designs. You will work closely with design, simulation, and functional verification teams to ensure product reliability, safety, and compliance with specifications.

Key Responsibilities:

• Develop and execute formal verification plans for digital blocks and systems.
• Identify key properties and invariants for verification using formal methods.
• Write formal specifications using SystemVerilog Assertions (SVA), PSL, or other formal languages.
• Analyse formal verification results, including counterexamples and traces, and collaborate with design teams to resolve issues.
• Integrate formal methods into the overall verification strategy alongside simulation and emulation.
• Document verification methodologies, results, and best practices.
• Work with EDA tools such as JasperGold, Questa Formal, OneSpin, or similar.
• Stay updated with the latest advancements in formal methods and apply them to improve verification quality and efficiency.

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Solid understanding of digital design principles, including RTL design (Verilog/SystemVerilog, VHDL).
• Experience with formal verification tools and methodologies.
• Strong knowledge of logic, Boolean algebra, and formal specification languages.
• Familiarity with common bus protocols and microarchitecture concepts.

Non UK nationals are welcome to apply to the position. Visa sponsorship and relocation will be supported for the successful applicant if coming from overseas.