Functional Verification Engineer
North Rhine-Westphalia, Germany
Permanent
€70,000 - €85,000 depending on experience
V-188430-1
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Lucy Edmondson
ASIC | Verification | DFT - EU
A semiconductor company that designs the microprocessors powering Supercomputers is looking for Verification Engineers to be involved with the development of products and to work on cutting-edge technology using methodologies at the state of the art.
You will be involved in verification of products built around the highest performance cores and the latest standard protocols. As a verification engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure highest-level systems that performance. Your work will involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.
As the successful Verification Engineer you have a visible impact on the product development and report to the verification manager. You have the opportunity to be a driving force of the verification effort. Your day-to-day work will entail the following:
You will be involved in verification of products built around the highest performance cores and the latest standard protocols. As a verification engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure highest-level systems that performance. Your work will involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.
As the successful Verification Engineer you have a visible impact on the product development and report to the verification manager. You have the opportunity to be a driving force of the verification effort. Your day-to-day work will entail the following:
- Reading and analysing the system requirements and architecture requirement documents
- Plan for functional verification activities for a given subsystem/functionality
- Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++
- Tests writing in embedded C and debug
- Participation to verification methodology improvements
- Project milestones and deliverables planning with respect to functional verification
- Organise work and deliverables between skills, internal and external teams
- Opportunities for mentoring and training junior Verification Engineers
- Opportunities to manage teams from external partners
- Verification and/or design of complex SoC
- Experienced in one or some of the following:
- SystemVerilog/UVM/VHDL, SystemC/C++, Embedded C
- Some previous experience in Firmware based verification is a good to have
- Experience in metrics driven verification
- Bash/Perl/Python
- Experience with verification management tools