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IP Support Engineer

Canada, North America,
San Jose, California,
Boston, Massachusetts,
Austin, Texas

Permanent

Base + Stock + bonus scheme + hybrid & remote working

V-194976-1

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ASIC Design Engineer – IP

Cambridge/UK remote - All seniorities welcome.

I am seeking a skilled IP Support Engineer to join my client who are leading the industry on cutting-edge AI technology.

As the successful IP support Engineer, you will join a team of technologists who have developed a high-performance RISC-V CPU from scratch and share a passion for AI and a deep desire to build the best AI platform possible. They are a computing company with an impressive roadmap and a VERY promising future, comprised of a truly world-class team of AI and CPU Engineers.

Acting as a technical IP champion, the experienced IP Support Engineer works with the design team to generate customised IP collaterals, manage IP releases and deliveries to customers, manage IP SW releases, create IP documentations, and support customers with technical debugging and manage customer bugs.

Responsibilities
  • Work with the IP R&D team to test the IP drops, generate custom IP collaterals, test the SW releases, create the technical documentation including integration guide, programming guide and releasing the IP for customer drops.
  • Interface between customers and R & D to escalate requests for improvements and provide a good understanding of customer needs.
  • Owns all customer technical issues, utilising all available resources to resolve those issues and achieve customer production.
  • Helps customers with module level and system-level integration issues, providing local technical and logistical support to insure successful adoption.
Experience & Qualifications
  • 5-10 years of experience in designing or developing IPs and SoC
  • Relevant front-end digital IP and ASIC design experience, from RTL, Verification to synthesis
  • Working knowledge of SoC architecture, including CPU, Interfaces (from JTAG to AMBA),
  • Experience with IP frontend CAD tools (Lint, CDC, Simulation) and backend tools (Synthesis, Equivalence/FEV, Timing, Place and route) 
  • Familiar with the entire chip development process including DFT (scan insertion, MBIST and LBIST), floor-planning, timing closure, power estimation, IR analysis, etc.
  • Knowledge of Functional Safety requirements
  • Knowledge of UVM
  • Knowledge of IP test methodologies
This role is based in the UK and you must have UK working rights to be eligible for the position. The role can be based in Cambridge or remotely from with the United Kingdom.

On offer is a competitive base salary, stock options and a bonus scheme.
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