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PLL Technical Lead

Paris, Île-de-France


€70,000+ depending on experience


I am seeking a dynamic and experienced Analog Designer to take on the role of PLL Analog IC Technical Lead.

This engineer will contribute to the chip/block level architecture definition and implementation.
In this role, the candidate will technically drive analog work-packages to deliver a state-of-the-art Integrated Circuit (IC) in deep submicron CMOS technology.
Work description
  • Focus on the architecture and design of high performance RF PLL.
  • Lead and support analog design work-packages from transistor schematic to GDSII
  • Participate, in close collaboration with the other project technical leaders, to the definition of the IC architecture and verification methodology.
  • Participate to discussion with customer on product architecture and specification definition.
  • Drive the architecture definition of the analog part(s) under his/her responsibilities.
  • Drive, in close collaboration with the analog design and layout team, the specifications of the IC analog sub-blocks to get the best area/power/performance trade-off
  • Work in close collaboration with the layout team to define the floorplan strategy to meet the stringent performance (e.g. speed, matching…) requirements
  • Contribute to the design and verification methodology at chip level and sub-blocks level
  • Define the test strategy of the analog part(s) under his/her responsibilities and drive its implementation
  • Participate to the evaluation of the fabricated IC in our measurement lab
  • Work in team to successfully design a state-of-the art IC
  • Animate design reviews
  • Write documentation in accordance with company Quality Assurance policy
Qualification and Experience
  • You have a MSc or PhD in Electrical Engineering or equivalent and 10+ years of hands-on experience in chip-level and circuit-level architecture definition, transistor level design and verification
  • You have a solid background in low jitter LC based PLL design on integrated circuit for high-speed and high-performance ADC/DAC data converters.
  • You have string experience in PLL design in advanced node CMOS/FDSOI silicon technologies (22nm and beyond)
  • You have a very good vision of the entire analog/mixed-signal IC design flow from transistor schematic to GDSII
  • You have a strong experience in mixed-signal IC project and technical leader role
  • You have an experience in the design of high-speed, low noise and interference robust analog and mixed-signal circuit
  • You have solid knowledge of analog design and simulation tools (Cadence Spectre)
  • You are creative and proactive
  • You demonstrate good analytical and problem-solving skills
  • A strong experience with Cadence design flow is necessary
  • A strong experience with EM tools is necessary
  • You are a team player with a critical attitude and sense of initiative
  • You communicate fluently in English (oral and written)

Please contact Parm Shergill to discuss this position further.
Apply now