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Principal Verification Engineer

Poland, Europe

Permanent

Excellent salary + bonus + relocation

V-197930

We are hiring for a Principal Verification Engineer to join our phenomenally successful Semiconductor IP client based in Krakow, Poland.

Our client has achieved global success and is transforming the way SoCs (System-on-Chip) are designed and verified. They are expanding multiple design centres, including Krakow, and seek a Principal Verification Engineer to work as the technical lead for verification activities. The Principal Verification Engineer will lead advanced UVM testbench development and debug, drive and execute RTL verification test/coverage at system level and be central in refining the verification process and methodology across the business.

Hybrid working is standard, with a few days in the office each week.

Requirements for the Principal Verification Engineer position include:
  • A Master’s degree or PhD in Electronics Engineering or similar
  • An extensive background within digital IP / SoC verification
  • Expert skills in SystemVerilog / Verilog, and UVM
  • Excellent problem-solving and team working skills
You can expect to enjoy working in a highly innovative, inspiring, friendly environment, that encourages productivity and creativity.

Our client offers highly competitive packages and relocation assistance where needed.

For details, please contact Caroline Pye.
Apply now
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