R&D Design Manager (ASIC - FPGA HW, CPU Architecture & SW)
Sophia Antipolis, France
Permanent
€80-100k + bonus + RSUs (dependent on level of experience)
V-199312
Rob Hudson
ASIC | Verification
Working for a major player in the semiconductor industry...This is a unique and complex technical management position. It would suit a senior level design engineer / architect or team lead / manager, who wants to progress their career in a brand new, and technically highly-challenging ASIC IP development environment.
Within the role, you would be responsible for guiding a team of highly skilled software and hardware engineers - across design, verification, architecture and software development & integration for complex semiconductor products.
Applicants MUST have EU working rights / ability to work in France, as sponsorship is not preferred.
I am looking to speak with senior level - technical / leadership engineers with a background in high-speed digital products and / or CPU or processor related technologies.
Must have skills:
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Within the role, you would be responsible for guiding a team of highly skilled software and hardware engineers - across design, verification, architecture and software development & integration for complex semiconductor products.
Applicants MUST have EU working rights / ability to work in France, as sponsorship is not preferred.
I am looking to speak with senior level - technical / leadership engineers with a background in high-speed digital products and / or CPU or processor related technologies.
Must have skills:
- University degree - BSc / MSc / PhD in Electronics, Microelectronics, Physics or Computer Science
- Industry experience in RTL design / RTL coding / digital design / hardware design - for FPGA / ASIC (VHDL and / or Verilog, System verilog)
- Architecture / micro-architecture
- System design & integration, system architecture
- SOC / IP integration for complex embedded processors - ARM / RISC-V
- Good communication skills in French & English
- Strong design experience within any of the following: Memory Systems - DDR / HBM, cache coherency / embedded CPU, firmware, Custom ISA
- Skills in system C / C / C++ / high level synthesis
- Excellent coding and automation skills - APIs, CI/CD, DevOps, OpenCL etc
- performance / modelling/ simulation
- memory systems - DDR, HBM
- Experience in Graphics, AI or CPU Processor designs would be preferred; however our client is open to reviewing individual profiles who have experience in one or more of the following areas: e.g. lidar sensors / IPU / IMU / VPU - vision processors / AI vision sensors / hardware accelerators / VPU - vectors / GPU algorithms / computer arithmetic
- Definition of complex architecture
- High-speed digital connectivity and protocols - Serdes, ethernet, USB, PCIe, AMBA / AXI, MAC, PHY, cache coherency - MESI, CHI
- CPU / GPU / VPU / RISC-V architecture
- Digital Verification (UVM / system verilog)
- Formal verification methods - Jasper Gold, C / system C
- Testing / validation
- Matlab / Simulink modelling experience
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