RTL Verification Lead Engineer - FPGA / UVM
Utrecht, Netherlands
Permanent
€60-80k depending on experience
V-188304
This job has now closed, click here to view similar opportunities
Rob Hudson
ASIC | Verification
Working for a cutting edge company, focusing on a complex processor for quantum computing technology.
This is a brilliant opportunity for a senior verification engineer to join them.
As Lead Verification Engineer, you will be tasked with leading ASIC / FPGA verification duties, and developing the UVM environment.
Must-have experience:
This is a brilliant opportunity for a senior verification engineer to join them.
As Lead Verification Engineer, you will be tasked with leading ASIC / FPGA verification duties, and developing the UVM environment.
Must-have experience:
- Circa 10 years' experience in digital or AMS verification
- VHDL / SystemVerilog
- RTL design / coding
- ASIC / FPGA digital verification knowledge
- Tcl / Python or similar coding / scripting
- UVM
- Previous experience setting up or developing a UVM environment.
- embedded software
- DevOps / software automation / CI/CD
- Other verification packages (e.g. OVM, OSVVM, Cocotb)
- Formal verification
Related roles
Search all our jobsVP Engineering (ASIC HW & SW)
South Holland, Netherlands
Permanent
Competitive salary + start-up benefits / shares
Read more
Digital IC Design Lead
South Holland, Netherlands
Permanent
€75-95k + shares
Read more
GPU Architect - (AI / CPU / RISC-V)
Greece, Europe
Permanent
€80-100k + bonus + RSUs + benefits (DOE)
Read more