RTL Verification Lead Engineer - FPGA / UVM

Utrecht, Netherlands


€60-80k depending on experience


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Working for a cutting edge company, focusing on a complex processor for quantum computing technology. 

This is a brilliant opportunity for a senior verification engineer to join them.

As Lead Verification Engineer, you will be tasked with leading ASIC / FPGA verification duties, and developing the UVM environment.

Must-have experience:
  • Circa 10 years' experience in digital or AMS verification
  • VHDL / SystemVerilog
  • RTL design / coding
  • ASIC / FPGA digital  verification knowledge
  • Tcl / Python or similar coding / scripting
  • UVM
(Nice-to-have experience):
  • Previous experience setting up or developing a UVM environment.
  • embedded software
  • DevOps / software automation / CI/CD
  • Other verification packages (e.g. OVM, OSVVM, Cocotb)
  • Formal verification
*Visa sponsorship is available