Senior Analog IC Layout Engineer

This is an opportunity for an experienced Senior Analog IC Layout Engineer to work for an established leader in energy efficient chip solutions.

Based in Reading, UK the Senior Analog IC Layout Engineer will be responsible for custom layout and verification of Analog circuits, cells, blocks, and IP for multi-Gigabit high speed SerDes up to and beyond 28Gb/s and/or memory IO in advanced semiconductor technology nodes.

Other responsibilities include:

• Layout and verification of high-speed Analog circuits
• Working closely with the design team to understand requirements and implement solutions
• Support IP and chip level integration
• Interact with customers on requirements and IP delivery
• Exposure to flip-chip package technologies

Experience is required in some or all of the following;

• Custom Analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or high frequency circuits
• Layout of high-speed or high frequency circuits such as; amplifiers, oscillators, phase-locked loops, delay-locked loops, biasing, buffers, regulators, filters, data converters
• Layout approaches and techniques for high-speed circuits, matching constraints, minimisation of parasitics, power grids and ESD requirements
• Modern semiconductor process technologies including 28nm, 14/16nm, 7nm
• EDA tools for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc

Take the next step in your career—contact Leon Morrison at IC Resources today:

Phone: +44 (0)208 400 2483