

Parm Shergill
Web | Mobile | UX - Contract
A multi national Semiconductor company is looking to hire a Senior CAD Engineer to participate in the design and manufacture of low-noise/low-power MEMS-based microphones and related audio solutions for their site in Switzerland. Candidates with a work permit for Switzerland will be considered (permit C or EEA nationals). The role is office based in the Zurich area.
As a member of the CAD team you will create and support innovative physical design methodologies and CAD flows for Analog/Mixed-Signal design. You will be hands-on, heavily involved in day-to-day design/layout issues to provide timely solutions and develop, maintain, and support utilities to improve productivity.
Responsibilities
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As a member of the CAD team you will create and support innovative physical design methodologies and CAD flows for Analog/Mixed-Signal design. You will be hands-on, heavily involved in day-to-day design/layout issues to provide timely solutions and develop, maintain, and support utilities to improve productivity.
Responsibilities
- Support, enhance, and maintain PDKs and various Analog/Mixed-Signal design tools
- Develop software for automation in Skill, Perl, Python, Unix Shell scripting
- Create documentation and provide hands-on training for design and layout engineers
- Work with EDA vendors to track and resolve issues
- Work with Technology Foundry teams (external/internal) to facilitate debugging and proper characterisation of tool related issues
- Optimise license mix/usage and support license negotiations
- Cadence tools: ADE-L/XL, Maestro, Spectre, Virtuoso Layout, Xcelium, APS, AMS, MMSIM, Assura
- Mentor tools: Calibre/PERC, Questa ADMS/Prime, afs, Symphony
- Experience in all phases of CAD tools from evaluation, QA, test, release, and user support to documentation
- Solid background in programming skills, circuit design, and device physics knowledge to help solve circuit design, layout, physical verification, and post-layout extraction challenges and problems
- Understand various aspects of partition level PNR including floor planning, power planning, placement, timing/power optimisation, CTS, routing, UPF
- Understanding and exposure to extraction and timing analysis flows
- Familiarity with chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.
- Experience with and good understanding of Cadence/Mentor license models
- Strong interpersonal/communication skills
- BS/MS in EE/CS or equivalent with 7+ years of experience
