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Senior CAD Engineer

Switzerland, Europe

Permanent

Depending on experience

V-195665

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Parm Shergill

Analog | Mixed Signal | RFIC Design - EU

I am recruiting for a multinational semiconductor firm that seeks to hire a Senior CAD Engineer to contribute to the design and production of low-noise/low-power MEMS-based microphones and related audio solutions at their Switzerland site. Consideration will be given to candidates with a valid work permit for Switzerland (permit C or EEA nationals). The position is based in the Zurich area.

As a member of the CAD team, you will be instrumental in developing and supporting innovative physical design methodologies and CAD flows for Analog/Mixed-Signal design. This hands-on role involves addressing day-to-day design/layout challenges promptly, as well as creating, maintaining, and supporting utilities to enhance productivity.

Responsibilities:
  • Support, enhance, and maintain Process Design Kits (PDKs) and various Analog/Mixed-Signal design tools.
  • Develop automation software using Skill, Perl, Python, and Unix Shell scripting.
  • Generate documentation and provide hands-on training for design and layout engineers.
  • Collaborate with EDA vendors to identify and resolve issues.
  • Work with Technology Foundry teams (external/internal) to facilitate debugging and proper characterisation of tool-related problems.
  • Optimise license mix/usage and participate in license negotiations.
Qualifications:
  • Proficient in Cadence tools: ADE-L/XL, Maestro, Spectre, Virtuoso Layout, Xcelium, APS, AMS, MMSIM, Assura.
  • Familiarity with Mentor tools: Calibre/PERC, Questa ADMS/Prime, afs, Symphony.
  • Experience across all stages of CAD tools, including evaluation, QA, test, release, and user support.
  • Strong programming skills with a solid background in circuit design and device physics knowledge.
  • Understanding of partition level Place and Route (PNR), including floor planning, power planning, placement, timing/power optimisation, CTS, routing, and UPF.
  • Exposure to extraction and timing analysis flows.
  • Knowledge of chip-finishing issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.).
  • Experience with and understanding of Cadence/Mentor license models.
For further details and application, please contact Parm Shergill.
Apply now
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